Memory structures may experience failures due to, for example, errors in memory cells. Some memory cell errors can be identified by testing, but current testing is insufficient to address errors that arise after memories have been manufactured or shipped, and/or the testing has undesirable overhead (e.g., cost, hardware, and/or latencies).
Methods of correcting and recovering from memory cell errors exist, but to achieve a high level of error correction, systems require excessive additional hardware (e.g., additional error correction (ECC) bits for each addressable word). Achieving a high level of error correction increases the costs of producing memories, increases memory access latency, and may also occupy coveted die area that could be used for other purposes.